Browse Prior Art Database

Control Store Reliability Enhancement Using Complement/ Re-complement Techniques

IP.com Disclosure Number: IPCOM000107607D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 120K

Publishing Venue

IBM

Related People

Fidishun, PC: AUTHOR

Abstract

The basic cycle time for a digital computer is determined by the time required for the longest single cycle path in the machine. In a micro- programmed computer the longest single cycle path is likely to be through the control storage unit, especially in cases where CMOS arrays (which are slower than bipolar arrays) are used. Time to do ECC detection and correction is not generally available without lengthening the cycle time, the result of which is lowered performance.

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This is the abbreviated version, containing approximately 52% of the total text.

Control Store Reliability Enhancement Using Complement/ Re-complement Techniques

       The basic cycle time for a digital computer is determined
by the time required for the longest single cycle path in the
machine.  In a micro- programmed computer the longest single cycle
path is likely to be through the control storage unit, especially in
cases where CMOS arrays (which are slower than bipolar arrays) are
used.  Time to do ECC detection and correction is not generally
available without lengthening the cycle time, the result of which is
lowered performance.

      This article discloses a method that allows stuck faults or
long- term intermittent faults to exist in any array while the array
is operating normally.  It allows multiple errors to exist and can be
implemented to provide a high degree of multiple bit failures as will
be described below.  It does require additional bits in the array,
but the number required is less than ECC techniques.  It also
requires an additional gate delay in the readout path.

      Consider a storage unit made of W words each containing B bits.
Assume each word is partitioned into Z zones.  An extra bit is added
to each zone within a word and will be called the C/R bit for the
zone.  For simplicity, the operation will be described for a single
zone consisting of all the bits in a word.  In an actual embodiment,
multiple zones would provide multiple bit failure coverage, and the
members of each zone would be chosen considering the failure modes of
the array, and would include packaging considerations such as chip
boundaries.  The figure shows an array with one zone per word with
its associated C/R bit and the connection to Exclusive OR (XOR)
circuits on the output of the array.

      In an all good array, the R/C bit in each word is set to
a logical ZERO and each output passes through its XOR logically
unaltered.  If a stuck-fault is detected (using parity circuitry or
other methods not shown here), the machine is stopped and the word
containing the error is re-loaded in ones complement form - including
the R/C bit, i.e., all bits are inverted.  The machine is restarted
and when the complemented word is read, the data passing through the
XOR circuits on the output is reinverted causing the normal data to
be presented with the bad bit corrected.

      Consider how this correction is accomplished.  If the error
occurred because a bit in the word was stuck to a ONE state and the
bit was required to be a ZERO, the complemented form of the data
would store a ONE in the position stuck to a ON...