Browse Prior Art Database

Managed Interrupt Status Queue and Auto Vector Generator for Personal Computer Systems

IP.com Disclosure Number: IPCOM000107620D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 5 page(s) / 232K

Publishing Venue

IBM

Related People

Farrell, JF: AUTHOR [+4]

Abstract

Described is a programmable device for use with personal computer systems equipped with the integrated service digital network (ISDN) used with the Micro Channel*. The device provides a programmable managed interrupt status queue and auto vector generator for the basic data rate adapter.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 29% of the total text.

Managed Interrupt Status Queue and Auto Vector Generator for Personal Computer Systems

       Described is a programmable device for use with personal
computer systems equipped with the integrated service digital network
(ISDN) used with the Micro Channel*.  The device provides a
programmable managed interrupt status queue and auto vector generator
for the basic data rate adapter.

      The device is designed to manage the interrupt status queue and
to provide an auto vector generator for the integrated ISDN module
(IIM) basic rate adapter.  The programmable feature allows the
microcode to acknowledge several interrupt status words per vector
generated, or a single interrupt status word per vector.  A
strappable feature allows either manual or auto vector generation
depending on which microprocessor system the IIM is running under.
It allows selection to be compatible with the interrupt status queue
manager and vector generator.

      The IIM contains two classifications of registers:  The first
class includes those registers which are common across all channels.
The IIM configuration register (ICR) and the vector holding register
(VHR) are common registers used for initializing the IIM after
power-on and for diagnostic purposes thereafter.  The only exception
is the VHR which is accessed by microcode during interrupt
processing.  The second class of registers includes those registers
which are channel or time slot specific and are replicated for each
time slot.  In the IIM, each channelized register is replicated six
times, once for each time slot.  The four IIM registers used are the:
a) channel configuration register (CCR); b) high level data link
control (HDLC) protocol configuration register (HPCR); c) channelized
error interrupt status register (CEISR); and d) end of process
interrupt status register (EOPISRO1 - EOPISR16).  The HPCR and the
CEISR are channelized registers.

      The ICR normally is written only during power-on diagnostic and
initialization.  However, it can be read or written at any time.  The
ICR is used to place the IIM in a variety of modes.  It is a
common register and is not replicated across time slots.  On a
hardware reset, all bits in the ICR are set to zeros.  Fig. 1 shows
the field of the ICR.  Only the queue mode (QM) bit and the BVEC bits
are of interest, the other bits in the ICR are not shown.  The QM and
the BVEC bits are used as follows:
      . EOPSR Queue Mode (QM) - 1 bit
           - 0 = single vector per status word in queue.
           - 1 = single vector, multiple status words in queue.
             Both modes are supported independent of whether the IIM
is used in autovector or manual vector mode. Selection of autovector
or manual mode is a function of use of the interrupt acknowledge
(IAK) pin on the chip. Manual vectors are generated when the IAK pin
is used. The IIM defaults to autovector mode if the IAK pin is
strapped...