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Method of Detecting a Cache Miss in Bi-level Cache Hierarchy

IP.com Disclosure Number: IPCOM000107626D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Capps Jr, L: AUTHOR [+8]

Abstract

Described is a circuit design for bi-level cache hierarchy microprocessor computer systems that provides the ability to detect cache miss for either level 1 or level 2. The design also allows selectivity as to which level is to be monitored so as to provide flexibility in monitoring cache activity.

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Method of Detecting a Cache Miss in Bi-level Cache Hierarchy

       Described is a circuit design for bi-level cache
hierarchy microprocessor computer systems that provides the ability
to detect cache miss for either level 1 or level 2.  The design also
allows selectivity as to which level is to be monitored so as to
provide flexibility in monitoring cache activity.

      Typically, in microprocessor-based systems it is common to
provide an external cache, or second level cache, in addition to an
internal, or first level cache.  When using a second level cache, the
need can arise in which software must be able to determine whether a
level 1 or a level 2 cache miss has occurred.  In prior art,
circuitry was employed to provide the software with the cache miss
information.  However, this circuitry was limited to single-level
cache designs.

      The concept described herein improves on the prior art design
by providing circuitry to allow the software to detect when either a
level 1 or a level 2 cache miss has occurred. The figure shows a
block diagram of the detection circuit.  The operation begins with
signals A, B, and C as inputs to module 10.  The A signal is used
to inform microprocessor 11 and module 10 that a cacheable memory
address is present and that the current cycle is to be converted into
a level 1 cache fill.  The B and C signals are data buffer control
signals and are used to indicate that a read cycle is in progress.
Module 10 combines si...