Browse Prior Art Database

Hybrid Algorithmic Pattern Generation

IP.com Disclosure Number: IPCOM000107629D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 89K

Publishing Venue

IBM

Related People

Koprowski, TJ: AUTHOR

Abstract

This article describes a technique whereby a combination hardware and software (hybrid) approach is used to generate algorithmic patterns on a logic tester to test memory devices.

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Hybrid Algorithmic Pattern Generation

       This article describes a technique whereby a combination
hardware and software (hybrid) approach is used to generate
algorithmic patterns on a logic tester to test memory devices.

      In the past, integrated circuits were classified as either
logic or memory.  Separate testers were developed and optimized to
test the appropriate devices.  Logic test requires large sequences of
unrelated patterns and the latest logic testers have large per-pin
memories which are used to store and apply these patterns which were
generated on a host computer and loaded onto the tester.  Memory test
is usually algorithmic and memory testers were developed to generate
the test data locally on the tester using APG (Algorithmic Pattern
Generation).  The latest integrated circuits can no longer be
classified as logic or memory as both are contained on the same chip.
Logic testers are now required to test memories along with the logic.

      Data used to test memories is usually algorithmic in nature.
When this data is expanded to test memories on VLSI logic testers
which do not have APG capability, the data volumes become quite large
and impact tester throughput. However, the cost of adding full
hardware APG capability is prohibitive.

      In many memory test sequences, only the address generation is
algorithmic in nature.  The memory data patterns and controls are
fairly simple and straightforward. The Hybrid APG approach was
developed based on this information and concentrates on hardware
algorithmic generation of the memory addresses and utilizes the
existing per-pin memories to supply the data patterns and controls.

      Fig. 1 shows the high-level block diagram of the Hybrid APG
approach.

      Fig. 2 shows the Address Gener...