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Speed Up Diodes Integrated into a Complementary BICMOS Technology for use in an Emitter Follower Circuit

IP.com Disclosure Number: IPCOM000107632D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 94K

Publishing Venue

IBM

Related People

Ogura, S: AUTHOR [+2]

Abstract

Given a fully complementary BICMOS technology (i.e., one offering pnp as well as npn bipolar transistors in addition to CMOS), the standard configuration for logic applications of a 2-way NAND gate is shown in Fig. 1A, implemented using an emitter follower type circuit. It has been found that if two diodes, each having Vf = 0.6 V, are added in series between the bases of the npn and pnp transistors (as indicated in Figs. 1A and 1B), performance of the circuit improves. This comes about because the voltage offset introduced by the diodes eliminates a "dead zone," or period of inactivity, which occurs while the pnp base node changes potential.

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Speed Up Diodes Integrated into a Complementary BICMOS Technology for use in an Emitter Follower Circuit

       Given a fully complementary BICMOS technology (i.e., one
offering pnp as well as npn bipolar transistors in addition to CMOS),
the standard configuration for logic applications of a 2-way NAND
gate is shown in Fig. 1A, implemented using an emitter follower type
circuit.  It has been found that if two diodes, each having Vf = 0.6
V, are added in series between the bases of the npn and pnp
transistors (as indicated in Figs. 1A and 1B), performance of the
circuit improves.  This comes about because the voltage offset
introduced by the diodes eliminates a "dead zone," or period of
inactivity, which occurs while the pnp base node changes potential.

      These diodes can be easily fabricated in such a fully
complementary BICMOS process described in the IEDM Technical Digest,
p. 485, 1990.  Furthermore, they can be easily integrated into the
FET drain area, sharing the diffusion with the bipolar extrinsic base
region.  This results in high density, without any additional
processing.

      A typical layout of the 2-way NAND is depicted in Fig. 2.  The
diodes are shown by dotted lines.  As will be described, they are
fabricated in much the same way as an emitter-base assembly.

      The diodes are fabricated in such a way as to resemble emitter/
base assemblies, so the layout is not complicated beyond what
structures would normally exist in the a...