Browse Prior Art Database

Enhanced Detection Method

IP.com Disclosure Number: IPCOM000107641D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Aichelmann Jr, FJ: AUTHOR

Abstract

A method is proposed which provides a way to detect multiple bit chip output failures in the same ECC word.

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This is the abbreviated version, containing approximately 100% of the total text.

Enhanced Detection Method

       A method is proposed which provides a way to detect
multiple bit chip output failures in the same ECC word.

      Conventional low-end memory applications use
single-error-correction (SEC/DED) codes for multiple bit output
chips.  These multiple bit outputs are used in the same ECC word.
This practice can result in not being able to detect all the data bit
failures without a packet detect code.

      This proposal provides a way to enhance or overcome this
limitation by adding an additional chip to check for these failures.
Figure 1 depicts the conventional SEC/DED with multiple bits per chip
in an ECC word.  Figure 2 shows the additional chip added to the
conventional application which provides a parity chip for the
detection of multiple bit chip out failures.