Browse Prior Art Database

SIMM Refresh

IP.com Disclosure Number: IPCOM000107651D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Aichelmann Jr, FJ: AUTHOR

Abstract

A method is proposed which provides an efficient low power refresh mechanism for both multi-sided and stacked SIMMs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

SIMM Refresh

       A method is proposed which provides an efficient low
power refresh mechanism for both multi-sided and stacked SIMMs.

      DRAM applications require a periodic refresh to maintain valid
data.  This refresh cycle typically consists of an address and a RAS
signal to the DRAM.  A SIMM is a grouping of chips packaged on either
side which can be stacked and plugged into a connector attached to a
memory array card.  These packages generally have multiple groupings
of RAS controls to support various increments of memory.  The
existing SIMM specifications do not recommend that these increments
or groups be refreshed at the same time because of delta current
peaks, noise generation, and EMI effects.

      This method provides a more efficient refresh mechanism by
separating the refreshes so that the different groups are overlapped.
Figure 1 depicts an example of a SIMM package with stacked chips on
both sides.  Each group is refreshed with separate non-overlapped RAS
cycles.  Figure 2 shows the way this proposal would overlap these
refreshes by offsetting each of these groups by the time it takes for
the refresh current to have peaked at the start of each RAS signal
start.  The current decays after the start and then increases again
when the RAS signal goes inactive finally returning to a standby
level.