Browse Prior Art Database

Base Non maskable Interrupt Register System

IP.com Disclosure Number: IPCOM000107661D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Andrews, LP: AUTHOR [+3]

Abstract

This article describes a method and hardware implementation to reduce the software overhead on a microprocessor bus architecture by having only one device on the bus contain a base non-maskable interrupt (NMI) register for detecting error information pertaining to all devices on the bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Base Non maskable Interrupt Register System

       This article describes a method and hardware
implementation to reduce the software overhead on a microprocessor
bus architecture by having only one device on the bus contain a base
non-maskable interrupt (NMI) register for detecting error information
pertaining to all devices on the bus.

      Some microprocessor bus architectures have a single error
signal, such as an NMI, without the use of vectors to identify which
device on the bus is detecting the error, and thus informing the
system software which device to read the error register from.  In a
system such as this, the error handling software must read the error
registers of each device on the bus to determine what error(s) has
occurred. This error handling procedure requires a large software
overhead.  This is especially so in systems where soft errors are
occurring and the application is capable of continuing once the error
has been compensated for.

      Presented herein is a method to reduce the software overhead by
having only one device on the bus contain a base NMI register.  This
base NMI register contains the error information required by the
system software pertaining to all devices on the bus.  Therefore, a
single read to this register during an NMI cycle is all that is
required for obtaining the information pertaining to the current
error condition(s).  Existing signal lines on the processor bus are
time division multiplexed with error information from the other
devices, thus no e...