Browse Prior Art Database

Coating Layer Thickness Reduction in Triplate Structures

IP.com Disclosure Number: IPCOM000107663D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Chang, CS: AUTHOR [+3]

Abstract

This article describes a new design of the PO layer in a triplate structure, as seen in Fig. 1, such that the same characteristic impedance of the signal lines on the S1 layer can be achieved. This will improve the cost and yield of the coating process, as well as those of the via hole making.

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Coating Layer Thickness Reduction in Triplate Structures

       This article describes a new design of the PO layer in a
triplate structure, as seen in Fig. 1, such that the same
characteristic impedance of the signal lines on the S1 layer can be
achieved.  This will improve the cost and yield of the coating
process, as well as those of the via hole making.

      Fig. 1 shows the cross-section of a typical triplate structure.
A coating technique is used to form the dielectric layer between S1
and PO.  In order to achieve a characteristic impedance of a signal
line on the S1 layer roughly equal to that on the S2 layer, the
coating layer thickness should be equal to the dielectric thickness
between the S2 and P1 layers.  In current designs, these dielectric
thicknesses are approximately equal to the width of the signal lines.

      From process considerations, it is desirable to have thick
layers of dielectric material between S2 and P1. However, it is
difficult to obtain a thick layer between PO and S1.  The number of
coatings required would be too costly.  Furthermore, the diameter of
the via hole connecting the PO layer to the S1 layer is approximately
linearly proportional to the thickness of this coating layer.  This
leads to a density concern.

      It is disclosed here that the PO layer over the long distance
signal lines on the S1 layer be etched into long strips in parallel
to the S1 signal lines.  Assume the S1 signal lines run in the
x-direction.  The PO layer in the fan-out region and beyond the
fan-out region will be handled as follows:
      (1)  Fan-out patterns to interconnect the chip C4 pads to the
...