Browse Prior Art Database

Microprocessor Interface for Serial EEPROM Devices

IP.com Disclosure Number: IPCOM000107665D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 9 page(s) / 378K

Publishing Venue

IBM

Related People

Kunkel, TJ: AUTHOR [+5]

Abstract

Currently, several vendors offer serial EEPROM devices to address non- volatile storage needs. Unfortunately, the interface to these devices is extremely slow (100 KHz) and can utilize a great deal of the interfacing microprocessor's bandwidth. This article describes an interface which utilizes direct memory access (DMA) to reduce the required microprocessor bandwidth significantly, while maintaining flexibility, thus allowing the use of a variety of vendor EEPROMs. (Other devices exist which use the same serial protocol and can be driven by this interface.)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 20% of the total text.

Microprocessor Interface for Serial EEPROM Devices

       Currently, several vendors offer serial EEPROM devices to
address non- volatile storage needs.  Unfortunately, the interface to
these devices is extremely slow (100 KHz) and can utilize a great
deal of the interfacing microprocessor's bandwidth.  This article
describes an interface which utilizes direct memory access (DMA) to
reduce the required microprocessor bandwidth significantly, while
maintaining flexibility, thus allowing the use of a variety of vendor
EEPROMs.  (Other devices exist which use the same serial protocol and
can be driven by this interface.)

      A variety of serial EEPROM devices are currently available on
the market with various memory densities and page sizes.
Nonetheless, the interface to these devices is typically composed of
two signals: a clock signal and a data signal.  The clock signal is a
unidirectional signal from the microprocessor interface to the serial
EEPROM.  This clock signal does not run continuously; in fact, clock
pulses are only generated when valid data is present on the data
signal.

      The data signal is a bidirectional signal which allows data to
be driven by the interface, during a write operation, or driven by
the serial EEPROM during read operations.  The data signal driver in
the interface and the serial EEPROM is an open collector device and
logic one states are provided via a pull-up resistor.  Utilizing both
clock and data signals, the microprocessor interface can support up
to eight devices.

      The memory read and write operations utilize a protocol which
places the clock and data signals into one of four states.  These
states, shown in Fig. 1, are Start Bit, Stop Bit, Logic Zero and
Logic One.  Building upon these four states, a read or write
operation is conducted in the following manner.
Read Operation
Current Address Read

      A current address read operation, shown in Fig. 2, begins with
a start bit being applied to the EEPROM device. Next, the slave
address is transmitted to the EEPROM; most significant bit first.
This slave address is composed of a four-bit device identifier, a
three-bit device address and a read/write bit.  Therefore, assuming a
device identifier of 1010B and a device address of 000B, the slave
address should be A1H.  Device identifiers are assigned by the
manufacturer of the device and may vary.

      Following this transmission, the EEPROM will acknowledge the
transfer by driving the data line to a logic zero state.  This
acknowledgement assures the device has been properly addressed.
After this acknowledgment, eight clock pulses are supplied to the
EEPROM and, with each clock pulse, it will supply a bit of the byte
at the current address, beginning with the most significant bit.

      If additional bytes are to be read, a logic zero state should
be supplied to the EEPROM.  This state acknowledges the receipt of
the first byte and requests a second. ...