Browse Prior Art Database

Representation of Controlling Clocks in Logic Networks Using Clock Derivation Logic

IP.com Disclosure Number: IPCOM000107667D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 94K

Publishing Venue

IBM

Related People

Sage, JM: AUTHOR [+2]

Abstract

Disclosed is a Design Rules Checker (DRC) which represents both the individually identified Level-Sensitive Scan Design (LSSD) clocks and the internally derived clocks in a manner which is consistent with the checking of the LSSD logic design rules.

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Representation of Controlling Clocks in Logic Networks Using Clock Derivation Logic

       Disclosed is a Design Rules Checker (DRC) which
represents both the individually identified Level-Sensitive Scan
Design (LSSD) clocks and the internally derived clocks in a manner
which is consistent with the checking of the LSSD logic design rules.

      To properly check a circuit's compliance with the LSSD design
rules for proper clock usage, it is imperative that for each logic
gate in the network all clocks controlling the gate in question be
known.  With the use of clock derivation logic, where multiple output
clock signals are derived from a single clock input signal, it is no
longer sufficient to represent only the explicitly identified LSSD
test clocks.  The derived clocks must be simulated and represented as
separate individual LSSD clocks.

      A bit string is created for every logic block on the part to
denote which clocks control the block.  There is a bit position for
each individual clock which does not feed any clock derivation
circuits.  Additionally, there are bit positions for each output
group of each clock derivation network per individual explicitly
identified clock which feeds the clock derivation network.

      An example is shown in Fig. 1 with five explicitly defined
clock Primary Inputs (PIs).  Three of these feed to Clock Derivation
Networks (CDN).  The first CDN has three output groups and is fed by
one clock PI.  CDN #2 has four output groups and is fed by two clock
PIs.  Three bit positions are required to represent the derived
clocks for Clock PI #1 and four bit positions for the clocks
associated with Clock PI #2.  Since clock PIs #3 and #4 do not feed
any CDNs, only one position is needed for each of these clocks. Four
bit positions are required for the clocks associate...