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Conditional Execution in a Register Management Scheme for Out of Sequence Execution

IP.com Disclosure Number: IPCOM000107668D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 6 page(s) / 365K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+4]

Abstract

A method for exploiting parallelism is known in which the set of architected register names is mapped into a larger set of physical names. Using this larger set of names allows many physical locations to be aliased to the same architected name, thereby permitting different logical instances of a common name to coexist. This facilitates a limited form of single-assignment data-flow.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 17% of the total text.

Conditional Execution in a Register Management Scheme for Out of Sequence Execution

       A method for exploiting parallelism is known in which the
set of architected register names is mapped into a larger set of
physical names.  Using this larger set of names allows many physical
locations to be aliased to the same architected name, thereby
permitting different logical instances of a common name to coexist.
This facilitates a limited form of single-assignment data-flow.

      What is novel about the above is that a method is presented for
restoring the machine state in the event of an interrupt, and thus,
interrupts can be precise in an out-of-sequence environment.  The
recovery mechanism, although straightforward, is somewhat costly in
terms of machine cycles.  Set forth below is a mechanism for
recovering prior machine state rapidly.  This rapid recovery
mechanism requires the storage of machine state at the decode time of
each instruction that could possibly be rolled-back.  Since
interrupts are infrequent, but almost any instruction has the
potential of generating one, this current mechanism is not advocated
for interrupts.  Rather, this mechanism is targeted at the
Branch-Wrong-Guess (BWG). The BWG differs from the interrupt in that
the BWG is a frequent event, e.g., one out of four instructions is
capable of generating one.  Thus, the storage overhead is not
prohibitive, and the recovery speed is imperative for BWG.

      In the known method above, a register renaming system is
proposed which is comprised of seven elements.  A Decode Register
Assignment List (DRAL) is a table that is used by the decoder to map
architected register names to physical array names.  An Array is the
set of physical storage elements that are used in place of a register
set.  An Assigned Array Position List (AAPL) is a bit vector that
indicates assignment for each element of the array, i.e., it
indicates that some active instruction has a pointer to that given
element.  An Array Loaded List (ALL) is a bit vector that indicates
whether or not each assigned array element has been loaded, i.e.,
whether the contents of the element are valid.  An Instruction Queue
(INQU) is a FIFO queue of information pertaining to each active
instruction. Instructions are decoded in order and endopted in order,
and the INQU is used to preserve this order.  A Final Register
Assignment List (FRAL) is a table that is analogous to the DRAL, and
is used for garbage collection (via the AAPL) as instructions leave
the INQU to endop.  A pending store buffer holds stores issued to the
memory by instructions that are represented in the INQU.  A pending
store is not released until the instruction that generated the store
successfully leaves the INQU.

      An entry in the INQU consists of four fields (five if
conditional execution is permitted).  The first two fields are an
architected register name and the corresponding physical array name
that is used...