Browse Prior Art Database

Detection of Intermixing of Discretely Derived Clocks

IP.com Disclosure Number: IPCOM000107670D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 94K

Publishing Venue

IBM

Related People

Sage, JM: AUTHOR [+2]

Abstract

Disclosed is a method for extracting the information needed to identify a potentially disastrous intermixing of internally generated clock signals (or clock and data signals) using the LSSD DRC (Level-Sensitive Scan Design Design Rules Checker) generated clock mask and a pair of subscripted arrays which are populated prior to the clock mask generation.

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Detection of Intermixing of Discretely Derived Clocks

       Disclosed is a method for extracting the information
needed to identify a potentially disastrous intermixing of internally
generated clock signals (or clock and data signals) using the LSSD
DRC (Level-Sensitive Scan Design Design Rules Checker) generated
clock mask and a pair of subscripted arrays which are populated prior
to the clock mask generation.

      It is advantageous to have the generation of product clocking
signals performed by the products themselves.  One specific
implementation of this is known as SCAT (Self-Contained Array
Timing).  With the incorporation of SCAT onto a part it is now
possible to generate a series of critically timed pulses designed to
clock a logical array and its associated buffer latches in a
race-free manner when a single package primary input is pulsed.

      The method by which LSSD DRC detects when the signals from two
or more SCAT clock generation circuits which are fed by the same
clock PI are intermixed will now be explained.  It is essential that
this condition be detected in that the logic timing at the point of
intermixing and all subsequent logic points is unpredictable.  This
may cause miscompares at the tester when test patterns generated by
Automatic Pattern Test Generators are applied and measured.

      In the following algorithm, illustrated by example in Fig. 1,
clock masks (which represent two logic signals feeding the block of
interest) contain clocks derived from different clock derivation
networks driven from the same clock primary input.
      Given:
      o    Two bit strings of equal length MASKA and MASKB in which
each bit position represents either an LSSD designated or derived
clock.
      o  ...