Browse Prior Art Database

Slit Channel Field Effect Transistors

IP.com Disclosure Number: IPCOM000107677D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Wang, LK: AUTHOR [+2]

Abstract

In a FET device the applied field from the gate produces both the substrate charges and channel charges. But only the channel charges will contribute to the device current. The transistor transconductance can be substantially increased by this channel current enrichment. A typical example is the thin silicon SOI FETs exhibit much higher transconductance by limiting the substrate thickness and thus more efficiently use the field to generate channel charge density.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 69% of the total text.

Slit Channel Field Effect Transistors

       In a FET device the applied field from the gate produces
both the substrate charges and channel charges. But only the channel
charges will contribute to the device current.  The transistor
transconductance can be substantially increased by this channel
current enrichment. A typical example is the thin silicon SOI FETs
exhibit much higher transconductance by limiting the substrate
thickness and thus more efficiently use the field to generate channel
charge density.

      This invention uses a new structure (Figs. 1 and 2). The
channel region of the FET device is etched into slits in order to
form conducting channel on the sidewall of the slits. In this case,
each slit is equivalent to two FET transistors back to back with the
conductor in the trench as the gate electrodes (Fig. 3).  The FET
substrate thickness is limited by the patterned slit thickness which
is similar to two back to back SOI FETs laid vertically. With the
thickness of the slit is narrower than 2X the maximum depletion width
from the gate field, the additional field from the gate after
reaching full depletion will added to the increase of channel
charges, thus increasing the channel conduction current.

      This new device structure can be fabricated by forming slits
between source/drain perpendicular to the gate in a conventional FET
device by using advanced lithography and dry etching technology. The
deposited gate material will fill the trench...