Browse Prior Art Database

Separation of Gate Salicidation from the Source/ Drain Salicidation

IP.com Disclosure Number: IPCOM000107678D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 175K

Publishing Venue

IBM

Related People

Barmak, K: AUTHOR [+2]

Abstract

The two most commonly used self-aligned silicides (i.e., silicides formed by reacting a metal with exposed silicon) are CoSi2 and TiSi2 . Compared to other silicides, these silicides form in a relatively reproducible manner and have low resistivity. However, there are different problems associated with each silicide, and the simultaneous silicidation of the source/drain with the gates does not allow the silicide to be properly optimized on both the single crystal Si (source/drain) and the doped polysilicon gate. For example, Ti reacts slowly with heavily As-doped Si and the transformation to the low resistivity C54 phase is inhibited on submicron lines (1).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 43% of the total text.

Separation of Gate Salicidation from the Source/ Drain Salicidation

       The two most commonly used self-aligned silicides (i.e.,
silicides formed by reacting a metal with exposed silicon) are CoSi2
and TiSi2 .  Compared to other silicides, these silicides form in a
relatively reproducible manner and have low resistivity.  However,
there are different problems associated with each silicide, and the
simultaneous silicidation of the source/drain with the gates does not
allow the silicide to be properly optimized on both the single
crystal Si (source/drain) and the doped polysilicon gate.  For
example, Ti reacts slowly with heavily As-doped Si and the
transformation to the low resistivity C54 phase is inhibited on
submicron lines (1).  Hence, it would be desirable to increase the Ti
thickness, the annealing time and temperature for the formation of
this silicide on the gate without affecting the silicide on the
source/drain.  CoSi2, on the other hand, is relatively insensitive to
dopants and line width, but its formation on polysilicon is very
non-uniform resulting in penetration  of the gate polysilicon (2) and
degradation of the gate oxide.  It would be preferable to have
independent control of the gate polysilicon thickness, metal
thickness, annealing time and temperature relative to the
source/drain.

      Decoupling of the gate and source/drain silicides has been
previously reported (3,4,5).  In the cases where a gate silicide
(3,4) was patterned by RIE during the gate definition process, a low
resistance gate electrode resulted.  However, the gate RIE process is
more difficult and the sidewall oxidation after the gate etch can
result in degradation of the gate metal.  In other cases (5) only the
source/ drain was silicided.

      Here we present two process integration methods for forming
self- aligned CoSi2 on the source/drain and self-aligned TiSi2 or
CoSi2 separately on the gate.  In one scheme the silicide is first
formed on the gate and then on the source/drain.  In the other scheme
the order is reversed.
      1.   Self-Aligned Salicidation of the Gate Prior to
Salicidation of the Source/Drain

      The gate polysilicon is defined using a Si3N4 mask. After the
formation of the sidewall, the source and drain regions are oxidized
to form a thick enough oxide layer to prevent the reaction of the Ti
with the Si in the source/drain regions (Fig. 1a).  The silicon
nitride on the gate polysilicon is selectively removed in a hot
phosphoric etch, and blanket Ti is deposited (Fig. 1b).  C54 TiSi2 is
formed on the gate using the appropriate anneal and wet etch
conditions (1).  The first anneal can be done for longer times or at
higher temperatures than usual, since there is no lateral silicide
formation from the source/ drain junctions.  The surface of the TiSi2
is then converted to TiN (about 20 nm) using a 900~C, 1-minute, NH3
anneal (6) (Fig. 1c).  The TiN is a diffusion barrier, preventing Co
f...