Browse Prior Art Database

Hardware Solution for High Performance Stack Operations

IP.com Disclosure Number: IPCOM000107701D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 74K

Publishing Venue

IBM

Related People

Gibbons, DG: AUTHOR [+2]

Abstract

Disclosed is a device for efficiently controlling a hardware stack using off-the-shelf video RAM (VRAM) parts. The new hardware controller is designed to minimize the need for processor support or intervention in stack maintenance.

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Hardware Solution for High Performance Stack Operations

       Disclosed is a device for efficiently controlling a
hardware stack using off-the-shelf video RAM (VRAM) parts.  The new
hardware controller is designed to minimize the need for processor
support or intervention in stack maintenance.

      In the past, a medium scale integration approach was taken in
which only the most basic functions were provided, namely, copy VRAM
row and change VRAM row operations were supported.  All, more
sophisticated, operations required processor intervention to
accomplish a sequence of basic functions.  With the new method, the
elementary functions provided now include:
      -    Push single level on stack
      -    Pop single level from stack
      -    Push double level on stack (when multiple rows of VRAM are
needed to represent an entry in the stack)
      -    Pop double level from stack
      -    Copy single VRAM row
      -    Copy double VRAM row
      -    Increment row pointer
      -    Decrement row pointer
      -    Add class name
      -    Delete class name.

      The proposed method (see Fig. 1) uses an integrated controller
and generic off-the-shelf VRAM modules.  Thus, the actual dimensions
of the stack can be arbitrarily large. The important features of the
design are described below.

      A stack pointer register has been incorporated into the stack
controller. ...