Browse Prior Art Database

Samerow Method of Accessing Dynamic RAMS

IP.com Disclosure Number: IPCOM000107704D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 7 page(s) / 282K

Publishing Venue

IBM

Related People

Kollaram, PR: AUTHOR

Abstract

In conventional methods when a processor accesses dynamic random- access memory (DRAM) for instruction or data, Row Address Strobe and Column Address Strobe (Chip Select in case of Static Column Mode devices) are generated without regard to the address of the previous access. An observation of behavior of microprocessors reveals that memory accesses are made to DRAM cells with ascending or descending addresses with high probability.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 25% of the total text.

Samerow Method of Accessing Dynamic RAMS

       In conventional methods when a processor accesses dynamic
random- access memory (DRAM) for instruction or data, Row Address
Strobe and Column Address Strobe (Chip Select in case of Static
Column Mode devices) are generated without regard to the address of
the previous access.  An observation of behavior of microprocessors
reveals that memory accesses are made to DRAM cells with ascending or
descending addresses with high probability.

      The SAMEROW method of DRAM access is based on this probability
(see flow chart, Fig. 1).  In this method the row address of the
current memory access is compared to the one in the previous access.
The Row Address Strobe and the Column Address Strobe (or Chip Select)
are generated accordingly.  If the row addresses are the same, the
DRAM is quickly accessed in Page mode or Static Column mode. However,
if they are different, a penalty is paid in meeting RAS precharge
time.  Because of the high probability of occurrence of the same row,
this penalty is offset by the time gained in fast accesses.  Thus,
increased overall efficiency.

      To achieve a given performance one may use this method with
slower inexpensive DRAM devices and save costs.

      In recent years there has been a general trend in microcomputer
technology in enhancing their performance. This is by achieving fast
execution times and shortening machine cycles.  Of these two, the
latter demands memory with fast read/write access times.  Though some
static RAM devices meet this requirement, their real estate (bits/
square inch) and cost (price/bit) make their usage prohibitive where
large amounts of memory are required. Commercially available high
density DRAM devices are answers to the real estate and cost.
However, they are relatively slow by their very nature.  Dynamic RAMs
with page mode or static column mode yield fast access times in some
cases such as block transfers, by accessing RAM cells in the same
row.  However, if the accesses are not in block transfer mode, the
next access may or may not fall in the same row. Especially when
dynamic RAM is used as a program as well as a data storage in a
typical computer system, the accesses could be random, and hence
provide relatively slower access time.  In fast processors this may
introduce wait states to it and, hence, reduce the system throughput.

      Several techniques were evaluated for using fast dynamic RAM
with static column and page mode features, in an effort to operate a
processor with zero-wait state.  it was found not possible to do it
with conventional methods.  A new technique was developed, and it is
described in this article.

      PERFORMANCE IMPROVEMENT:  Use this technique to increase the
system throughput where the processor is fast, and memory is not fast
enough to avoid wait-state insertion.

      COST REDUCTION:  SAMEROW method of access reduces costs
because, with this tech...