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Conversion of Scenarios to Test Cases

IP.com Disclosure Number: IPCOM000107707D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 169K

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Related People

Barrett, KL: AUTHOR [+3]


This article describes a method of converting the scenarios produced by SMVX to low level test cases.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 43% of the total text.

Conversion of Scenarios to Test Cases

       This article describes a method of converting the
scenarios produced by SMVX to low level test cases.

      A state machine may be "simulated" by SMVX for all the valid
combinations of the inputs and desired initial states. These
scenarios consist of the combination of inputs and the state (along
with the resulting outputs).  These scenarios may be used in the
system level simulator as a list of scenarios to watch for during the
simulation of high level test cases; or they may be converted into
low level test cases that may be run on a "unit level" simulator.  A
unit level simulator is a model of the required piece of logic in
isolation from the rest of the system.

      A method of automatically converting the scenarios generated by
the expert system SMVX to low level test cases is disclosed.  The
scenarios are the combination of input signal values along with any
initial state information and the resulting output signal values.
These signals are represented as a list of units which participate in
the scenario.

      The signal units have a slot called the FAC_NAME and another
called the FAC_VAL that record the strings used to generate the
scenario in a human-readable form (must be acceptable to the
simulator).  These are printed one per line, separated by the default
connector " = ".  The FAC_NAME is the name of the signal that is
accepted as a facility name in the simulator.  The FAC_VAL is any
value assigned to the FAC_NAME that is valid for the simulator.

      The case of a scenario requiring a specification of values that
should not occur during a scenario (this case may arise due to a huge
number of desired values but a small number of undesirable values for
the scenario) is handled by assigning a value to the CONNECTOR slot
of the unit (e.g., FAC_NAME > 3 can be represented by putting the
value of " > " in the CONNECTOR slot of the unit).

      The list of scenarios that is generated by the expert system
SMVX is stored in an output file that is read by a subsidiary Lisp
function that reads the values of the FAC_NAME, CONNECTOR and FAC_VAL
slots of the units mentioned in every scenario.  The function has to
interact with the knowledge bases to receive this information.  Once
all the signals have valid units associated with them, then the
concatenations of the values of the slots FAC_NAME, CONNECTOR and
FAC_VAL are printed out to a test case file. The test cases also
contain a prologue for the unit simulator.

      The values of the output signals mentioned in the scenarios are
treated differently.  They are to be checked by the verification
program running the simulator; hence they are used to create
individual IF statements that assign the value of the facility at
simulation time to a variable and compare that variable with the
"expected" value mentioned in the scenario.  If the comparison
succeeds, then the next output signal is tested, if any...