Browse Prior Art Database

Early Prefetch Buffer

IP.com Disclosure Number: IPCOM000107709D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

A method is described for eliminating the dynamic penalty associated with prefetching dead lines.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Early Prefetch Buffer

       A method is described for eliminating the dynamic penalty
associated with prefetching dead lines.

      The three factors that influence the "goodness" of a prefetch
mechanism are coverage, accuracy, and timeliness. In general,
coverage can be increased by sacrificing accuracy, and accuracy can
be increased by sacrificing timeliness.  If timeliness is sacrificed,
the prefetch mechanism may not help performance at all, and thus,
sensible mechanisms attempt to trade off coverage and accuracy.  The
negative impact of poor accuracy is twofold, namely: memory traffic
is needlessly increased, and the pipeline experiences trailing edge
degradation as a result of needless prefetchting.  The problem of
increased memory traffic can be addressed by improving the memory
technology, i.e., by building memories with sufficient bandwidth to
allow for more traffic.  However, trailing edge degradation must be
addressed as a machine organization issue. Proposed is a buffer which
prevents unnecessary trailing edge from disrupting the pipeline,
thereby solving the trailing edge problem associated with low
accuracy prefetch mechanisms.

      A line buffer (Early Prefetch Buffer) should be placed near the
level one (L1) cache, and the prefetch mechanism should place
prefetched lines into this buffer instead of into the cache.  Thus,
the L1  cache is impervious to all prefetch traffic.  The prefetched
line should be moved from the buffer into the cache at the time of
the next miss.  If the next miss is a miss to the prefetched line,
then the Early Prefetch Buffer has the appearance of a zero cycle...