Browse Prior Art Database

New Process for Highly Integrated Bipolar Circuits

IP.com Disclosure Number: IPCOM000107710D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 5 page(s) / 168K

Publishing Venue

IBM

Related People

Subbanna, S: AUTHOR

Abstract

Disclosed is a process for highly integrated bipolar circuits, using collector-up HBTs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

New Process for Highly Integrated Bipolar Circuits

       Disclosed is a process for highly integrated bipolar
circuits, using collector-up HBTs.

      An N+ substrate is used.  An N-type epitaxial layer (10 micron,
1E17) is grown by high-temperature epitaxy.  They implant and diffuse
in the sub-emitter (using arsenic).  The sub-emitter is about 4
microns deep.  Next, an N layer (3E18, 100-200 nm) is grown
epitaxially. This N layer forms a lightly-doped emitter.  This is
followed by open bottom deep trench formation extending into the N+
substrate, using oxide sidewall and N-type polysilicon fill (Fig.
1A).  Shallow trench (or recessed oxide) isolation and recessed oxide
cap for the deep trench are formed next.  Next, a reach-through is
formed (using lithography, ion-implant and annealing - Fig. 1B).

      This is followed by a P+/N epitaxial stack grown by
low-temperature epitaxy.  A 25-50 nm P+ (4-6E18) layer forms the
base.  This layer also contains germanium, starting from 10% at the
emitter side, and increasing to 20% at the collector side.  The grade
silicon-germanium base serves to speed up electrons and increase the
speed of the device. The last N layer (2E17, 500 nm) forms the
collector region.

      Then an N+ collector contact layer is formed by
recrystallization of in-situ-doped (LPCVD) amorphous silicon.  An
oxide/nitride stack is then deposited (Fig. 1C).  This is followed by
lithography to define the collector.  The nitride, oxide, N+ contact
layer and part of the N collector layer are then etched.  An
oxide/nitride sidewall is formed.  P++ poly is deposited in the open
silicon areas, either by selective deposition, or by blanket
deposition and planarization, followed by patterning and etching.
The P++ layer is passivated by HIPOX, and a short anneal follows to
link up extrinsic and intrinsic base (Fig. 1D).

      Thick plasma oxide is then deposited and planarized, and
contact openings are defined and etched.  Standard BEOL techniques
can then be used to fill the contact holes and define the metal lines
(Fig. 1E).

      A representative 3-input ECL circuit is shown in Fig. 2A.  The
layout of the input 4-tr...