Browse Prior Art Database

Dynamic Adjustment in Processor Pipeline Based on Usage Pattern

IP.com Disclosure Number: IPCOM000107711D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+4]

Abstract

Current microprocessor designs have the ability to subcycle their pipelines as a means of interfacing to a different set of external requirements. Such a facility is extendible within a single design to select the "best" pipeline structure based on instruction interdependencies.

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Dynamic Adjustment in Processor Pipeline Based on Usage Pattern

       Current microprocessor designs have the ability to
subcycle their pipelines as a means of interfacing to a different set
of external requirements.  Such a facility is extendible within a
single design to select the "best" pipeline structure based on
instruction interdependencies.

      Let us consider a processor that can dynamically select between
two distinct pipeline structures. It does this by subcycling within a
given cycle and will issue instructions on a subcycle basis or a
cycle basis. The subcycle feature needs to be supported by additional
internal registers which affects the overall latency time, end-to-end
time, of the instruction.

      There are certain aspects of performance that depend on the
instruction issuance rate and there are certain aspects of
performance that depend on the instruction latency time. These latter
aspects can be classified as instruction interdependencies and
include:
o   Disable Overlap and Serialization,
o   Address Generate Interlock especially AGIL, where the input for
AGEN is set by a prior execution, and
o   Branch Wrong Guess recovery.

      In some cases the number of instructions in the pipeline
affects the occurrence of instruction interdependencies.

      Not all instruction interdependencies are known because they
are path dependent, and in the case of branches that are predicted by
a BHT, such a prediction success rate varies.

      If the instruction issuance rate is done at the expense of
instruction latency, then for certain instruction sequences one or
the other choice is preferable. The ability of a dynamic pipeline
structure to select the one or the other pipeline on the basis of
history can be preferable to any single use.

      The following poin...