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Compatible Clocking Circuit for Different Microprocessors used in Personal Computer Systems

IP.com Disclosure Number: IPCOM000107718D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 151K

Publishing Venue

IBM

Related People

Holness, SE: AUTHOR

Abstract

Described is a compatible clocking circuit arrangement wherein a correct microprocessor clocking phase is generated relative to a computer system's clocking phase so that different microprocessor types can be used in a personal computer (PC) system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 51% of the total text.

Compatible Clocking Circuit for Different Microprocessors used in Personal Computer Systems

       Described is a compatible clocking circuit arrangement
wherein a correct microprocessor clocking phase is generated relative
to a computer system's clocking phase so that different
microprocessor types can be used in a personal computer (PC) system.

      PC systems are often required the ability to function with
different microprocessor types in order to provide for increased
speed requirements.  For example, a PC system functioning at 25 or 33
MHz with one type of microprocessor must be compatible so as to
function with a different type of microprocessor operating at 25 or
33 MHz. Due to the clocking phases of different types of
microprocessors and the associated logic, a circuit is required to
compensate for the clocking differences for system compatibility.  In
this example, a PC designed to a microprocessor's clock input
specifications operating at 25 MHz will have to generate the correct
synchronization by adjusting the processor to the proper clock phase.
Another microprocessor operating at 25 MHz with a 50 MHz clock input
will also be required to adjust the microprocessor's clock phase to
remain compatible with the same PC system.

      Generally, a 25 MHz microprocessor requires a 50 MHz clock
input.  Internally, this microprocessor will divide the 2 times clock
by two forming a 1 times clock which it uses to determine the timing
of logic operations.  It assigns a phase 1 and a phase 2 to each of
the 2 times clock cycles within a 1 times clock cycle internally.
This assignment is aligned on the falling edge of a reset operation.
Externally, synchronization to the internal processor 1 times clock
can be accomplished by synchronizing the falling edge of the reset to
the proper external 1 times clock phase while meeting the
microprocessor's 2 times input timing specifications.  Another type
of 25 MHz microprocessor operates on a 1 times clock input, and
internally it doubles its input frequency to the 2 times value.  It
assumes that the PC system's logic operates with the same 1 times
clock input so that no microprocessor/system synchronization is
required.

      In prior art, a PC system designed to 1 times the
microprocessor input clock specifications had to generate the correct
clock synchronization by adjusting the microprocessor to the system
clock phase.  A 2 times input clock microprocessor will also need to
readjust the microprocessor's clock phase to remain compatible with
the system.  This is accomplished in the power platform complex by
sensing the power-up microprocessor's clock phase, which is random,
on the falling edge of the power-on reset signal. The system is reset
a second time after adjusting the processor clock to the correct
phase based upon the system clock, if needed.  The second reset is
required because the microprocessor needs a stable clock signal upon
exit of its reset state. The a...