Browse Prior Art Database

Update Mechanism for Personal Computer System Resident Firmware

IP.com Disclosure Number: IPCOM000107738D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 151K

Publishing Venue

IBM

Related People

Bealkowski, R: AUTHOR [+2]

Abstract

Described is an update mechanism for personal computer (PC) system resident firmware using reprogrammable device technology. The mechanism enables a device media, such as a diskette, to be used for updating in-line system firmware in areas which require changes, such as code changes and/or functional extensions.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Update Mechanism for Personal Computer System Resident Firmware

       Described is an update mechanism for personal computer
(PC) system resident firmware using reprogrammable device technology.
The mechanism enables a device media, such as a diskette, to be used
for updating in-line system firmware in areas which require changes,
such as code changes and/or functional extensions.

      In prior art, there was no mechanism to update in-line system
firmware, such as power-on self-test (POST) and basic input/output
system (BIOS), since the code was contained in read-only memory (ROM)
devices.  Typically, the code in the ROM was established when the ROM
device was manufactured and could not be changed.  There was an
inability to replace the ROM without an expensive field hardware
update and this precluded the ability to update the POST and BIOS of
the system.  However, as the size and complexity of system firmware
increases, there can be a need to update the ROM code after the
system is installed.

      In order to allow a ROM type of device to be erased and
reprogrammed without removing the part, an in-place reprogrammable
(IPR) device is used to provide a means of erasing and reprogramming
the ROM.  It is particularly effective for the large density
requirements.  IPR for system firmware updating is part of a
technology known as initial microcode load (IML), which allows for an
image of the system firmware to be read in from a device, such as a
diskette, at power-on time.  This image is copied into a portion of
the system's random- access memory (RAM) which is mapped into the
architecturally defined address space for POST and BIOS.  However,
one of the drawbacks of IML is that it relies heavily on a
substantial amount of already resident firmware and complex hardware,
such as the disk controller and drive.

      The concept described herein utilizes the IPR technology but
implements a mechanism that significantly reduces the amount of code
and hardware required to maintain an up-to-date copy of the system
firmware. The concept provides a means of always having a current
copy resident in the system and a load need only occur for up-dating
purposes.  The design for providing an IPR technique for the system
firmware is described in two parts:  first as an IPR device system,
as shown in Fig. 1; and second as an IPR control level flow diagram,
as shown in Fig. 2.

      In Fig. 1, microprocessor 1 has a core ROM 2 from which it
fetches instructions after a power-on reset.  Little support logic is
required to be initialized for microprocessor 1 to fetch instructions
from core ROM 2. Core ROM 2 contains the code which will test the
validity of the code residing in IPR device 3.

      In the IPR control flow diagram, as shown in Fig. 2, from the
initial power-on 21 state, the code in core ROM 2 (Fig. 1) performs
core hardware checkout 22...