Browse Prior Art Database

Personal Systems Functional Architectural Verification Methodology

IP.com Disclosure Number: IPCOM000107742D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 5 page(s) / 205K

Publishing Venue

IBM

Related People

Cabezas, JC: AUTHOR [+4]

Abstract

Described is a software facility designed for personal computer systems to test architectural functionality. The facility provides a common methodology for the development of functional verification and exerciser test programs.

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Personal Systems Functional Architectural Verification Methodology

       Described is a software facility designed for personal
computer systems to test architectural functionality.  The facility
provides a common methodology for the development of functional
verification and exerciser test programs.

      Functional architecture verification is provided by means of
exercise test programs.  Instruction/command sequencing, data
dependencies and feature options are tested.  The test programs range
from the very general to the very specific.  Operator tailoring of
parameter input allows for the specific testing of known problem
areas or the bypass of problem areas until a resolution is found.
Maximum test coverage is accomplished by the execution of these
programs with all options at their default values. This ensures a
worst-case test condition being presented and the largest number of
errors to be detected in a minimum amount of time.  Test case
coverage is further enhanced by the execution of multiple copies of
the program with variations of the parameter input.

      Since the objective of the test program is functional
verification, the exerciser test programs are divided into two
categories:
      a)   Functional testing of the adapter/device where the program
attempts to test all possible combinations of commands and data to
ensure the operation of the hardware.
      b)   Exercising the device by utilizing basic commands and
varying amounts of data to ensure that the adapter/device can handle
a variety of data sizes and amounts as well as varying data rates.

      The architectural verification and exerciser software facility
comprises a number of library services and supervisory tasks which
co-ordinate the operation of many hardware exerciser programs, which
in turn provide the architecture/hardware verification facility.
Fig.  1 shows a block-diagram system flow of the hardware exerciser.
The hardware exercisers are designed to verify architecture and
adapter device conformance to functional specifications and are
written to exercise all supported hardware functions in both valid
and invalid conditions.  If an adapter supports more than one device,
multiple instances of the exerciser are invoked to run devices
concurrently.

      There are three basic environments in which all hardware
exercisers are expected to execute.  In the first and most common
environment, the exerciser cycles so as to generate test after test.
In the second environment, the exerciser detects an error and issues
an error message with sufficient information to define the problem
and corrective action. The third environment involves interaction
between the user and the exerciser.  This occurs when the exerciser
is initially being debugged and also when a problem is being further
isolated or defined.

      The block diagram of Fig. 2 shows the various steps undertaken
by the hardware exerciser and is designed s...