Browse Prior Art Database

Gate Array Interface for Disk Controller

IP.com Disclosure Number: IPCOM000107744D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Bocchino, TA: AUTHOR [+5]

Abstract

Described is a gate array interface circuit configuration for personal computer (PC) systems that is designed to provide compatibility between diskette controller circuits and direct memory access (DMA) circuits.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 66% of the total text.

Gate Array Interface for Disk Controller

       Described is a gate array interface circuit configuration
for personal computer (PC) systems that is designed to provide
compatibility between diskette controller circuits and direct memory
access (DMA) circuits.

      The gate array interface circuit is primarily intended to be
used with the Intel 82077 diskette controller so as to provide
compatibility with DMA controllers which transfer only one byte of
data.  Diskette controllers, such as the 82077, contain a
sixteen-byte first-in, first-out (FIFO) buffer, such that there is a
possibility whereby a second or more bytes can be transferred if the
data from the diskette drive is not transferred in time.  Without
compatibility between the two controllers, a time-out condition can
occur.

      The concept described herein provides a gate array circuit
configuration that provides transfer compatibility between diskette
controllers, such as the 82077, and DMA controllers.  The circuit
configuration is in the form of a transformer module consisting of a
twenty-eight-pin design. The circuitry consists of two disk access
data registers, a mapping circuit and a diskette state machine to
monitor input/output (I/O) commands.  The pin connection designations
are shown in Fig. 1.

      In actual operation, when the state machine circuitry, located
within the transformer, detects a verify command, a -BURST signal
sent to the DMA controller is driven high to indicat...