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Interrupt Driven Task Scheduler for Imbedded Control Systems

IP.com Disclosure Number: IPCOM000107746D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 108K

Publishing Venue

IBM

Related People

Holley, EL: AUTHOR

Abstract

This article describes a task scheduling technique for use in a computer system and which is hardware or software interrupt-driven and is based on a standard subroutine call.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Interrupt Driven Task Scheduler for Imbedded Control Systems

       This article describes a task scheduling technique for
use in a computer system and which is hardware or software
interrupt-driven and is based on a standard subroutine call.

      Most task schedulers use a task state principle which usually
consists of three states (active, ready, and waiting).  Each state
consists of a queue or queues which manage tasks either on a first-
come, first-serve basis or on some priority basis with a priority
attached to a task. A task is in the 'active' state when it currently
is running on the CPU.  It is in the 'ready' state when it is ready
to be active but is not running on the CPU.  It is in the 'wait'
state when it is waiting for some asynchronous action to occur and
'post' or 'notify' the task so it can be placed in the 'ready' state.
The problem with this scheme is the overhead in computing time
required to manage the movement of tasks from one state to another.
Since a task can be moved to another state while in the middle of
executing a routine, a large amount of CPU time is required to switch
tasks.  The process of a 'waiting' task being 'posted' to resume
execution requires a large amount of CPU time and memory resources.

      The technique described in this article eliminates the concept
of a task being in a 'state' and, more importantly, waiting to be
'posted'.  This scheme describes a task not as a routine which can
switch back and forth between different states of running, but as a
single code routine which, when required to run, is called like a
standard subroutine (very little overhead) and stops execution when a
standard 'return' from subroutine is performed.  The task cannot wait
to be posted in the middle of execution, and is suspended only as the
result of a higher priority interrupt being received by the CPU.
Most modern CPUs can handle interrupts very efficiently.  A task is
called as the result of either a hardware or a software interrupt
occurring.  Because a task is treated like a normal subroutine, which
most CPUs can handle with very little overhead, an increase of at
least an order of magnitude in 'task swapping' rate can be achieved.

      The task scheduling technique disclosed herein can be described
as a dynamically replaceable interrupt handler mechanism using the
standard model of CPU interrupts.  In this model an interrupt causes
the CPU to stop execution of the current routine and proceed with a
routine called an interrupt handler.  The interrupt handler is
usually located by a vector table which is us...