Browse Prior Art Database

Multi-addressing Mode Microprocessor Memory Support for Personal Computers

IP.com Disclosure Number: IPCOM000107748D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 6 page(s) / 315K

Publishing Venue

IBM

Related People

Dayan, RA: AUTHOR [+3]

Abstract

Described is a personal computer interface facility to provide parameters in the support of an operating system (OS). It is designed to provide OSs with the capability of determining the amount of memory to support for systems which utilize multi-addressing-mode microprocessors.

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This is the abbreviated version, containing approximately 20% of the total text.

Multi-addressing Mode Microprocessor Memory Support for Personal Computers

       Described is a personal computer interface facility to
provide parameters in the support of an operating system (OS).  It is
designed to provide OSs with the capability of determining the amount
of memory to support for systems which utilize multi-addressing-mode
microprocessors.

      The amount of addressable memory supported by microprocessors
can vary depending on the addressing modes available.  Internal
components within a system may limit the amount of memory that is
supportable.  An OS may have to alter its memory management based
upon the capabilities of a particular system; otherwise, either
performance or data integrity will be sacrificed.  In order to
support several possible configurations, the basic input output
system (BIOS) and setup are required to supply information which
helps the OS decide what is the correct amount of memory to support.
The concept described herein provides a means whereby the OS can
determine how much memory to support based on the capabilities of the
hardware installed in the system.

      In certain microprocessors, up to one megabyte of memory is
used in a segmentation model.  As applications, networks and host
connections are developed and added to a system, the amount of user
memory that is available to the user is reduced.  Memory capacity can
actually become a constraint in the ability for a system to function.
To solve this problem, new modes of addressing were developed. This
new mode of addressing was developed to allow the user to address
sixteen megabytes of memory, but is not compatible with the original
mode, though similar. To operate in this mode, it is necessary to
place the microprocessor in protected mode.  To provide protected
mode operations for twenty-four bits of addressing, busses and
support chips were designed to meet twenty-four bits of addressing.
For example, a system direct memory access (DMA) chip which supports
data transfers to and from input/output (I/O) devices without
processor intervention can only handle data transfers within sixteen
megabytes of memory.

      With the advent of thirty-two-bit microprocessors, thirty-two
bits of addressing or four gigabytes of physical memory address space
became available.  Initially, all support chips attached to the
thirty- two-bit microprocessor only supported twenty-four bits of
addressing.  This only allowed access to sixteen megabytes of memory
address space. This constrained the full addressing capability of the
thirty-two-bit microprocessor.  As thirty-two-bit OSs became
available, both systems using the twenty-four-bit addressing and the
thirty-two-bit addressing had to be supported.  As a result, this
created problems with the OSs, such as an I/O buffer could not be
placed above the sixteen-megabyte boundary when the thirty-two-bit
microprocessor was operating as a twenty-four-bit microprocessor.

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