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High Efficiency Real Time Cyclic Redundancy Checker/ Generator for Integrated Services Digital Network

IP.com Disclosure Number: IPCOM000107753D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 143K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+2]

Abstract

This article describes a circuit arrangement for generating check bits in real time.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Efficiency Real Time Cyclic Redundancy Checker/ Generator for Integrated Services Digital Network

       This article describes a circuit arrangement for
generating check bits in real time.

      The difficulty with prior-art approaches can be demonstrated
with the aid of the timing chart of Fig. 2.  On the last bit of
the sub- multiframe (SMF) (2048th bit) four check bits have to be
generated and latched within time "a" and following that the
generator has to be reset (zeroed) within time "b" (C1-C4 have to be
reset to zero at the start of a new SMF).  Thus, in one clock period
(T) the check bits have to be generated, then latched, and then reset
in order.  This allows for very little latitude in design and very
critical timing constraints.  The circuit herein described allows for
greater design freedom and relaxed timing constraints (Fig. 3).  Fig.
1 shows the cyclic redundancy check (CRC) mainframe structure when
the frame counter increments, the SMF switch will change state.
Similarly, when the counter changes from frame #15 to frame #0, the
switch will toggle. Thus, the SMF switch serves both as a control for
the selector and as a SMF detector.  Operationally the circuit
disclosed herein is shown in Fig. 3, blocks 1A and 1C being
identical.  When 1A is calculating, 1C holds its value, and when 1C
begins to calculate, block 1A holds its value.  This is controlled by
the SMF switch,  Thus, the generators also act as their own latches
by holding their values.  As soon as block 1B captures the incoming
four check bits, a comparison can be done with the appropriate
generated bits.

      In its simplest form block 1B is a sixteen-bit shift register
which shifts in the first bit from the receive serial bit stream
(RSER) at the beginning of every frame (Fig. 1).  At bit 2 time of
frame #7 or frame #15 a comparison can be done.  Any time after the
comparison and before the start of the next SMF, the generator can be
zeroed out (one would be zeroed out in frame #7, the other in frame
#15).  Therefore, if "T" represents one bit time, there would be 255T
time following the capture to do a comparison and 254T time to zero
out the generator (there are 256 bits per frame, 32 time slots of 8
bits each).  Compare this with the timing constraints of Fig. 2, and
a design is seen virtually independent of technology an...