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Selectable Bus Parity for Microcomputer Channel Bus

IP.com Disclosure Number: IPCOM000107757D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Eng, RC: AUTHOR [+7]

Abstract

A technique is described whereby selectable data and/or address bus parity architecture is applied to microcomputers equipped with an input/output (I/O) and/or system bus so as to allow devices attached to the bus to determine, on an individual basis, if parity has been generated and checked.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Selectable Bus Parity for Microcomputer Channel Bus

       A technique is described whereby selectable data and/or
address bus parity architecture is applied to microcomputers equipped
with an input/output (I/O) and/or system bus so as to allow devices
attached to the bus to determine, on an individual basis, if parity
has been generated and checked.

      The selectable parity architecture provides a means of enabling
data bus and address bus parity to be made available, on an optional
or selectable basis, based on the operational capability of the bus
drivers and receivers of devices attached to microcomputers equipped
with an I/O and/or system bus.  The selectivity is determined on an
individual bus cycle basis whereby bus drivers/receivers may choose
not to implement bus parity, while others may choose to implement
parity so as to increase reliability and error detection capability.

      Implementation of data or address parity is recommended, but
not mandatory, for any bus master, slave, or system.  The bus parity
is designed to provide functional compatibility between those
participating devices supporting parity and those devices not
supporting parity.  The architecture is designed to allow the
following combinations of bus drivers and receivers:

      Bus Driver    Bus Receiver Parity Checked?
      Supports Parity     Supports Parity     Yes
      Supports Parity     No Parity Support   No
      No Parity Support   Supports Parity     No
      No Parity Support   No Parity Support   No
Implementation of the selectable parity is as follows:
o    Data Bus Parity -
       .   In the case of parity for the data bus, a parity signal
line data parity bit (DPARx) is provided on the bus for every byte of
bus data; each DPARx bit represents the parity bit for the
corresponding data byte.  A single data parity enable signal,
-DPAREN, is provided on the bus to indicate whether the data...