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Low Power Dynamic Random Access Memory Using On Chip Error Correction and Refresh Control

IP.com Disclosure Number: IPCOM000107768D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 93K

Publishing Venue

IBM

Related People

Bertin, CL: AUTHOR [+4]

Abstract

By substituting good redundant cells for weak (leaky) cells, then reducing refresh frequency, low standby power is achieved for dynamic random-access memory (DRAM). The method retests and optimizes refresh frequency each time the memory chip is powered up. Each chip in a system operates at its own refresh frequency for minimum power dissipation.

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Low Power Dynamic Random Access Memory Using On Chip Error Correction and Refresh Control

       By substituting good redundant cells for weak (leaky)
cells, then reducing refresh frequency, low standby power is achieved
for dynamic random-access memory (DRAM).  The method retests and
optimizes refresh frequency each time the memory chip is powered up.
Each chip in a system operates at its own refresh frequency for
minimum power dissipation.

      Column address select (CAS) before row address select (RAS)
refresh (CBR) is frequently used in DRAMs.  By building upon this
capability of a DRAM to control its own refresh cycle and adding
on-chip control by existing error correction code (ECC) as shown in
the figure, redundancy is used to replace cells causing short data
retention time and refresh cycle frequency is appropriately reduced.

      During manufacturer's device test, early fails are replaced by
redundant cells and refresh time is adjusted for the longest possible
retention time using signal margin test levels that assure
appropriate guard bands for high reliability.  The design includes an
architecture of appropriate data line inversions to store an all high
voltage, or "physical 1's" pattern including syndrome (ECC) bits, to
guarantee that all cells are properly stressed.

      During normal use, the CAS-before-RAS cycle is detected by
decoder DEC and output CBR is generated.  CBR steps counter C3 down
toward 0.  Ordinarily, an "=0" output from C3 is low, preventing CBR
from generating REF out of AND A3. When C3 reaches 0, REF is sent to
DRAM, performing a standard refresh operation using an internal
refresh address counter.  At the same time, counter C3 is loaded to
its initial value by counter C2.

      The value of counter C2 is set at system and chip and chip
initial program load (IPL) time.  Two basic input combinations for
special test modes are used at decoder DEC to genera...