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Hardware Support for an Operating System Timer

IP.com Disclosure Number: IPCOM000107777D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Blades, JA: AUTHOR [+4]

Abstract

Hardware support of operating system timer interrupts is disclosed. The hardware provides the capability for the microcode to generate interrupts. The microcode uses this capability to cause timer interrupts whenever certain events occur.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Hardware Support for an Operating System Timer

       Hardware support of operating system timer interrupts is
disclosed.  The hardware provides the capability for the microcode to
generate interrupts.  The microcode uses this capability to cause
timer interrupts whenever certain events occur.

      The hardware uses a single 32-bit counter with a period of 10
microseconds as the only timer.  The period of the timer is chosen to
be smaller than any required measurement and, in this case, is
actually close to the time required for the processor to service an
interrupt.  With 32 bits of resolution, the timer can run for almost
12 hours before wrapping.  In addition to this counter, a 32-bit
register contains a value which is constantly compared to the
counter, and another register contains a few bits which control how
interrupts are generated.  With this hardware implementation, the
microcode can support any number of events timed for any desired
length between the hardware timer period and several hours.

      When a request is made of the operating system to time an
event, the amount of time in timer periods is simply added to the
current value of the counter and the resulting value is compared to
the current compare register value.  If it is less, the current
compare value is inserted at the front of a queue and the new value
is loaded in the compare register.  Otherwise, the new value is
placed on the queue in order of stop value.  When the compare value
matches the count value, an interrupt to the processor is generated.
Th...