Browse Prior Art Database

Debug Facility for Multiple Chips in a Common Module

IP.com Disclosure Number: IPCOM000107784D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Eikill, RG: AUTHOR

Abstract

A method for debugging multiple-chip modules is disclosed. When multiple chips are fabricated in a common module, some of the critical control lines between these chips are not accessible outside of the module. These lines are very important for initial hardware verification and subsequent problem determination. As the number of chips in a module increases, the complexity of the module and the critical nature of these control lines also increases.

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This is the abbreviated version, containing approximately 61% of the total text.

Debug Facility for Multiple Chips in a Common Module

       A method for debugging multiple-chip modules is
disclosed. When multiple chips are fabricated in a common module,
some of the critical control lines between these chips are not
accessible outside of the module.  These lines are very important for
initial hardware verification and subsequent problem determination.
As the number of chips in a module increases, the complexity of the
module and the critical nature of these control lines also increases.

      The method to be described consists of the following. A set of
module pins is reserved for a multiplexed debug bus, and all chips
are allowed access to this bus.  Some common control logic is also
neces sary to ensure that all chips on the module will drive their
signals on this bus at the proper time.  The control logic includes a
set of scan-only latches that are decoded via chip hardware to form
driver enables.  These latches are implemented at a consistent
location in the scan ring of every chip resident on the module.  This
allows more efficient microcode control of the signals to be driven
off module (debug modes).  These latches are set to the same value in
all chips whenever they are loaded.  This is done to avoid any
conflict that could arise if the chips were not in consistent debug
modes (more than one chip driving the same debug bus signal).

      To avoid performance problems associated with timing critical
signals, auxiliary copi...