Browse Prior Art Database

Fast Monitoring of iAPX86 Processors under OS/2 and AIX

IP.com Disclosure Number: IPCOM000107785D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Cramer, A: AUTHOR [+3]

Abstract

It is often desirable to analyze the timing characteristics of processing systems and the software used therein. For this purpose, information on the monitored software has to be supplied to an external monitor via a hardware interface within a minimum of time. The method described in this article permits this in particular for processors of the Intel iAPX86 family and operating systems OS/2* and AIX*.

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Fast Monitoring of iAPX86 Processors under OS/2 and AIX

       It is often desirable to analyze the timing
characteristics of processing systems and the software used therein.
For this purpose, information on the monitored software has to be
supplied to an external monitor via a hardware interface within a
minimum of time.  The method described in this article permits this
in particular for processors of the Intel iAPX86 family and operating
systems OS/2* and AIX*.

      Before the monitoring of processing systems, "event" statements
are introduced in the software to be monitored. These statements
perform I/O operations which reach, for example, an external monitor
via an interface.

      In Intel processors of the iAPX86 family (from processor 80286
upwards), processes wanting to use I/O statements (Assembler: IN,
OUT) must be I/O privileged.  By the operating system, each code
segment is associated with one of four privilege levels.  The
respective privilege level decides which data segments may be
accessed by a code segment, which code segments may be invoked
therefrom, and, finally, whether I/O statements may be executed.  The
processor ensures by hardware means that such protective measures are
being observed.  In the case of an I/O privilege, this is done as
follows.  The flag register of the processor stores a value IOPL of 0
< IOPL < 3 in bit positions 12 and 13.  The privilege level of a
code segment wanting to execute an IN or OUT instruction must be
numerically less than or equal to the IOPL value.  In many operating
systems, only the operating system code is I/O privileged.  For event
statements it would therefore be necessary to develop an operating
system routine which handles I/O operations.  This, however, would
seriously affect the timing characteristics of the system being
monitored.

      Direct manipulation of the two bit positions in the flag
register of the processor...