Browse Prior Art Database

Controlled Collapse Chip Connection on Substrate Edge

IP.com Disclosure Number: IPCOM000107792D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 450K

Publishing Venue

IBM

Related People

Horbach, HG: AUTHOR [+4]

Abstract

The described three-dimensional VLSI chip packaging method allows memory and logic chips to be arranged within a minimum of space. This enhances the performance of computer systems, as the storage chips are readily accessible.

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This is the abbreviated version, containing approximately 53% of the total text.

Controlled Collapse Chip Connection on Substrate Edge

       The described three-dimensional VLSI chip packaging
method allows memory and logic chips to be arranged within a minimum
of space.  This enhances the performance of computer systems, as the
storage chips are readily accessible.

      The inventive concept is based on producing Controlled Collapse
Chip Connection (C4) Pb/Sn solder connections on the periphery of Si
carrier substrates (or single chips), by which the latter are
vertically soldered to the next packaging level (Fig. 1).

      Through-plating of the Si carrier from the front to the back
side permits chips to be mounted on both carrier sides. The chips are
linked with the substrate by the common solder connection on the
carrier edge.

      Vias for through-plating the substrate are KOH-etched into the
silicon.  The vias thus formed are V-shaped according to the Si
crystal orientation.  By protecting the regions not to be etched by a
photolithographically structured silicon nitride layer, clearly
defined V-trenches for complete through-plating may be produced from
the front and the back side.

      Pb/Sn solder balls are applied by means of the standard C4
production method.  After vapor deposition of a Cr/Cu/Au layer
through a metal mask (or overlying a polyimide or photoresist
lift-off structure), the Pb/Sn is applied within the vias.  A reflow
step ensures that the Pb/Sn covers the entire Cr/Cu/Au layer.

      In addi...