Browse Prior Art Database

Checking ECC Circuits

IP.com Disclosure Number: IPCOM000107796D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Badger, RL: AUTHOR [+5]

Abstract

Disclosed is a scheme of checking ECC (error correcting code) circuits to ensure proper functioning of the circuits. A (40,32) single error correcting and double error detecting code is used to illustrate the design.

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Checking ECC Circuits

       Disclosed is a scheme of checking ECC (error correcting
code) circuits to ensure proper functioning of the circuits. A
(40,32) single error correcting and double error detecting code is
used to illustrate the design.

      The ECC circuits are divided into three components: ECC GEN for
generating check bits, SYNDROME GEN for generating syndrome bits, and
ERROR CORRECT/DETECT for detecting and correcting errors.  The
checking designs for ECC GEN and SYNDROME GEN are shown in Figures 1
and 2.  The basic idea for the design is that the input parity should
agree with the output parity.  Figure 3 shows the checking design for
ERROR CORRECT/DETECT.  In the figure, NE, CE and UE are signals
representing no error, correctable single error, and uncorrectable
multiple error, respectively.