Browse Prior Art Database

Data Recovery in a Communication Channel using Out Of Phase Clocks

IP.com Disclosure Number: IPCOM000107846D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 143K

Publishing Venue

IBM

Related People

Ko, MA: AUTHOR

Abstract

Disclosed is a method for recovering data in a communication channel where the sender and the receiver are operating at the same clock frequency with an unknown phase difference.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 46% of the total text.

Data Recovery in a Communication Channel using Out Of Phase Clocks

       Disclosed is a method for recovering data in a
communication channel where the sender and the receiver are operating
at the same clock frequency with an unknown phase difference.

      The first step in recovering the received data is to determine
whether the receiver's clock leads or lags the sender's clock.  (The
phase detect circuitry for such a purpose can be constructed using
two flip-flops clocked by the sender's clock with the receiver's
clock as the data input for the first flip-flop and the output of the
first flip-flop feeding the second flip-flop.  The second flip-flop
is used to protect against metastability.  This setup allows the
phase difference to be determined in two clock cycles.)  The phase
detect output is locked as soon as valid data is sent since a
changing phase detect output can lead to data loss in the data
synchronization circuitry. This imposes a limit on the stability of
the sender's clock and the receiver's clock. Specifically, they
cannot drift by an amount large enough to cause set up or hold time
violations at the receiver when a maximum size packet is sent.  In
the following discussion, the clocks are assumed to have 50% duty
cycles.

      If the receiver's rising clock edge leads the sender's rising
clock edge by no more than half a clock period, the received data is
captured using the receiver's clock if the data is stabilized at the
receiver no later than half a clock period from the rising edge of
the sender's clock. Careful choice of drivers, such as Backplane
Transceiver Logic (BTL), can reduce the settling time delay.  If the
settling time and the line propagation delay are less than half the
clock period, the data is synchronized to the receiver's clock by
being captured using the receiver's clock.

      If the receiver's rising clock edge lags the sender's rising
clock edge by no more than half a clock period, the received data can
be captured using the falling edge of the sender's clock (assuming a
50% duty cycle) if the settling time and the line propagation delay
are less than half the clock period.  The data is synchronized to the
receiver's clock by capturing it again in a second register using the
receiver's clock.  The purpose of the first register is to allow
enough set-up time for the second register.

      A functional block diagram of the invention is shown in the
figure.  The output of the phase detect provides the select signal
for the multiplexer.  If the receiver's clock lags the sender's
clock, the output of the lagging edge register will be selected as
input to the leading edge register.  If the receiver's clock leads
the sender's clock, the incoming data will be selected instead.  The
lagging edge register captures data at the falling edge of the
sender's clock so that the data will meet the set-up time for the
leading edge register in those cases where the receiver's clock...