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Browse Prior Art Database

Hardware Stack Cache for Computer Systems

IP.com Disclosure Number: IPCOM000107853D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 152K

Publishing Venue

IBM

Related People

Genduso, TB: AUTHOR [+3]

Abstract

Described is a hardware stack cache for computer systems designed to improve run-time performance when executing high level system code. The design allows a register machine to operate like a stack machine when executing stack operations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 46% of the total text.

Hardware Stack Cache for Computer Systems

       Described is a hardware stack cache for computer systems
designed to improve run-time performance when executing high level
system code.  The design allows a register machine to operate like a
stack machine when executing stack operations.

      Generally, high level programming languages use the software
concept of stacks.  However, certain register-based computer systems
do not directly support stacks in hardware, but implement stacks in
memory through software instructions.  In these systems, stack
operational performance may not benefit from the use of processor
caches.  This is because stack operations tend to write first to the
stack and then read from the stack only once for each element of the
stack.

      Since conventional caches are designed for repeated access of a
data item, the software stack operation does not conform to the
concept of increasing the performance of cache operations.  As a
result, the concept described herein implements a hardware cache
aimed at increasing the performance of stack operations.  The idea of
a hardware stack cache should not be confused with the idea of a
stack machine.  The concept presented herein allows a register
machine to operate like a stack machine when executing stack
operations.

      Fig. 1 shows a block diagram of the basic structure of a system
which incorporates a hardware stack cache.  The structure introduces
four unique features, as follows:
     1) The structure significantly reduces the number of tags.  This
in turn reduces the amount of tag random-access memory (RAM)
necessary to perform the cache operations.
     2) The structure uses address pairs and a hash algorithm to
access the cache.
     3) A new cache protocol specifically for the stack cache is
introduced.
     4) The structure reduces the negative performance impact of the
stack operations on data or instruction caches.  This is be
cause stack operations tend to store and load from cache only once.

      Fig. 2 shows the structure of the stack cache.  In actual
operation, the stack cache can have multiple word cache lines.  The
stack cache can use either a write-in or write-through caching
policy.  However, for simplicity in explaining the stack cache
operation, the single word cache line and the write-in policy are
used.

      The hardware stack cache is composed of the following
components:
     - Stack Tag Set (STS) - Any number of STSs greater than one can
be used.  Four STSs are demonstrated, each STS is composed of the
following:  a) the top of stack (TOS) register; b) the bottom of
stack (BOS) register; c) the STS least recently used (LRU) bits; and
d) the STS 'In Use' bit to indicate if this STS is currently 'In Use'
or 'Not In Use'.
     - Data Array - RAM which contains the data is shown as a single
column, but is not limited to this geometry.
     - Data Valid Bit (DVB) - Indicates if t...