Browse Prior Art Database

Nitride Spacers to Improve Second Metal Coverage in a CMOS Process

IP.com Disclosure Number: IPCOM000107857D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Chanclou, R: AUTHOR [+4]

Abstract

Described is a method of forming nitride spacers on the side-walls of the first level metal lands to improve the coverage of the second metal layer to be subsequently deposited.

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Nitride Spacers to Improve Second Metal Coverage in a CMOS Process

       Described is a method of forming nitride spacers on the
side-walls of the first level metal lands to improve the coverage of
the second metal layer to be subsequently deposited.

      The problem is illustrated in conjunction with Fig. 1. The 700
nm thick level metal lands 11 are formed over an insulating
substrate, typically made of phosphorous-doped silicon glass (PSG).
Next, a thin 300 nm thick Si3N4 layer 12 is blanket deposited on the
structure.  Then, the thick (e.g., 1200 nm) second level metal is
deposited onto the structure forming layer 13. As apparent from Fig.
1, reliability defects, such as cracks 14, are often produced at the
edge step of the nitride layer when the slope angle thereof is higher
than 80o . The first level metal evaporation process can be optimized
to reduce the said slope angle, but in most cases, the second level
metal coverage still remains a source of potential problems.

      To eliminate any reliability exposure, nitride spacers along
the sidewalls of the first metal lands are produced in order to
reduce the critical slope angle. An AME 5000 tool is used for
deposition of a 440 nm thick nitride layer 15, and a Tegal 1511 tool
is then used for anisotropic etch. As a result, nitride spacers such
as 15 and 15b remain on the structure. The process is continued as
standard. The final structure is illustrated in Fig. 2. As apparent
in the latter, a reduced...