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Differential Receiver for High Common Mode Voltage Bus (EIA-485 Interface Receiver)

IP.com Disclosure Number: IPCOM000107861D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 115K

Publishing Venue

IBM

Related People

Flynn, DM: AUTHOR [+3]

Abstract

In establishing an interface between separate clusters of computing equipment it is frequently the case that these clusters will be referenced at separate and distinct electrical potentials. Due to the discrepancies which may exist in ground shifts and power supply configurations this potential difference may be of the order of several volts (i.e., five volts) or more. Under these conditions there is a particular electrical standard known as EIA-485 (EIA = Electronic Industries Association), which must be adhered to for proper operation of the interface.

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Differential Receiver for High Common Mode Voltage Bus (EIA-485 Interface Receiver)

       In establishing an interface between separate clusters of
computing equipment it is frequently the case that these clusters
will be referenced at separate and distinct electrical potentials.
Due to the discrepancies which may exist in ground shifts and power
supply configurations this potential difference may be of the order
of several volts (i.e., five volts) or more.  Under these conditions
there is a particular electrical standard known as EIA-485 (EIA =
Electronic Industries Association), which must be adhered to for
proper operation of the interface.

      Described herein is the design of a bus receiver circuit which
will meet the requirements specified by the EIA-485 standard.  The
salient features of the design are as follows:

      The receiver input voltage levels are differential in nature,
that is, the opposite phases of the input signal are present
simultaneously at separate I/O locations.

      The receiver differential input voltage sensitivity has a
minimum magnitude of 200 mV over the entire range of allowable bus
common mode voltage (-7V to +12V).

      In addition to the above primary performance requirements, the
design described herein also meets all additional requirements set
forth by interface standard EIA-485.  In addition, the particular
design disclosed herein has the added functional feature of input
threshold hysteresis.  This feature, although not required for EIA-
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