Browse Prior Art Database

Software Recovery of Page Faults on Microprocessors with Integrated Memory Management Units

IP.com Disclosure Number: IPCOM000107866D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 180K

Publishing Venue

IBM

Related People

Desai, D: AUTHOR [+2]

Abstract

This article describes a technique for use in a microprocessor that manages paged memory presence validation by master with an integrated memory management unit (MMU) such as that of the Intel 80386 CPU.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 42% of the total text.

Software Recovery of Page Faults on Microprocessors with Integrated Memory Management Units

       This article describes a technique for use in a
microprocessor that manages paged memory presence validation by
master with an integrated memory management unit (MMU) such as that
of the Intel 80386 CPU.

      The Intel 80386 family of processors and Motorola processors
have integrated memory management units that allow for vastly
increased memory addressing and a virtual memory scheme based on
segmentation and paging.

      Intel processors operating in Protect Mode divide programs into
uniform size pages (4 KB) which bear no direct relationship to the
logical organization of the programs, though the programs still
retain linear, contiguous views of memory.  Bus masters, which
provide addresses directly to memory without intervention from the
processor, must work within the system paging environment without the
benefit of the main processor's MMU.

      A scheme whereby bus masters moving large quantities of data
across page boundaries are assisted by a combination of software and
hardware that allow them to operate within paging with little cost is
described in [*].  One drawback to that solution is that the software
must pin the pages being used by the bus master, i.e., these pages
are not allowed to be swapped out of memory.  This restriction is
necessary because the Intel family of 80386 processors is architected
with integrated MMUs, and page faults are processed entirely on chip.

      In systems with limited amounts of main memory, potentially
large percentages of memory may be unavailable to the paging system.
It is desirable to operate in an environment where pages used by bus
masters become unpinned and available for swapping.

      In the technique disclosed herein the channel operated by the
bus master to assist in page boundary crossings accesses the table of
page entries.  However, when a boundary crossing occurs, the channel
not only loads the new high-order bits of address, but it also checks
the presence bit of the entry to determine whether the page is
actually in main memory.  If the page is currently in main memory,
processing continues normally; however, if the page is absent, an
external interrupt is generated for the 80386 processor as an
external page fault interrupt.

      The interrupt service routine examines the information
contained in the page table entry of the page generating the fault
for the location of the page on the hardfile.  Using this address, it
brings the page into main memory and resets the external page fault
interrupt, allowing the bus master to resume processing.

      This technique dispenses with the pinning requirement (*) and
allows the system to process external page faults. The only
restriction is that either the boundary crossing mechanism must use
the system page table to insure coherency, or the device driver
managing the bus master transfer mu...