Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Method and Design for Applying Stuck Faults in an LSSD Boundary Scan Environment

IP.com Disclosure Number: IPCOM000107872D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 3 page(s) / 126K

Publishing Venue

IBM

Related People

Douskey, SM: AUTHOR

Abstract

Applying stuck faults to chip I/O during early lab testing to verify the hardware error detection and isolation circuitry and code is a common practice. The ability to apply these "bugs" is becoming increasingly limited through the use of multi-chip modules (MCMs). Similarly, the limited probe-point capability these size factors have created has led to the introduction of boundary scan.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method and Design for Applying Stuck Faults in an LSSD Boundary Scan Environment

       Applying stuck faults to chip I/O during early lab
testing to verify the hardware error detection and isolation
circuitry and code is a common practice.  The ability to apply these
"bugs" is becoming increasingly limited through the use of multi-chip
modules (MCMs).  Similarly, the limited probe-point capability these
size factors have created has led to the introduction of boundary
scan.

      This discussion modifies the boundary scan latches to continue
to function as tester probe points in both the random pattern
self-test and chip-to-chip interconnect environments, but
additionally be programmable into stuck faults during lab error-path
verification testing.

      Boundary scan latch configurations come in three basic forms:
-  "functional" latches in series with the data path
-  "flush-thru" latches in series with the data path
-  "muxed" latches parallel to the data path.

      In all cases, they are designed to sample the data from inside
the chip and drive data to the chip's internal logic. Direct I/O
drive control, a common attribute of these three configurations,
allows all designs to be enhanced for stuck signal drive control.
For illustration purposes, the "flush-thru" will be discussed.

      Fig. 1 shows the common I/O boundary scan SRL being used in the
AS/400*.  In functional mode the DRVCLK and the RCVRCLK are always
active and the test L2 is inactive, putting the SRLs in "flush-thru"
mode.  During internal chip random pattern self-test the DRVCLK is
allowed to pulse to sample internal patterns, while the RCVRCLK is
held inactive to prevent external conditions from affecting the test.
In external chip-to-chip interconnect test, the RCVRCLK is allowed to
pulse while the DRVCLK is held inactive; thus external signals are
sampled.  Note that the receiver L2* and both L1s are required for
these three modes.  The enable L2, labelled "test" is required only
for scan purposes. This test L2 will be used for our new boundary
scan driven, simulated, stuck I/O test function.

      Note in Fig. 1 the addition of an AND to the DVRCLK path.  This
allows the test L2 to degate the clock to both the driver and enable
L1.  When the test L2 is a '0', the latch functions as before, but
when a '1', the DRVCLK is degated, freezing the value in both the
enable and driver L1.

      A stuck fault is applied by scanning the test L2 to a "1",
blocking the DRVCLK from changing the data and enable state of the
L1s. The driver and enable L1s are scanned at the same time to the
values needed for the various stuck faults available. With the enable
L1 at '1', the driver...