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Minimum Size L1/L2 Combination

IP.com Disclosure Number: IPCOM000107874D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 125K

Publishing Venue

IBM

Related People

Cook, PW: AUTHOR [+2]

Abstract

This article describes a CMOS L1/L2 latch which utilizes a single clock line due to the use of transfer gates. Its features include skew-free feedback with a minimum of clocking connection, and it allows for gated clock extensions in a simple manner. INTRODUCTION

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Minimum Size L1/L2 Combination

       This article describes a CMOS L1/L2 latch which utilizes
a single clock line due to the use of transfer gates.  Its features
include skew-free feedback with a minimum of clocking connection, and
it allows for gated clock extensions in a simple manner.
INTRODUCTION

      LSSD Latches are needed in any large design.  The essence of
such a latch is:
      $    The A-Clock (controlling the shifted input).
      $    The B-Clock (controlling the L1/L2 transfer).
      $    The C-Clock (controlling the data input).

      The L1 and the L2 must both be fully static latches, that is,
they must both be capable of holding data for extended periods when
the clocks are down.  Additionally, size and speed are important
criteria, since the smaller the latch, the higher the density on the
chip, and the faster the latch, the higher the chip performance.  A
L1/L2 combination is demonstrated whose area is equal to 3 2-input
NOR gates, and whose setup time is equal to 2 inverter delays.

      Any static latch involves three elements:
      .    Active inputs which are gated by the input clocks.
      $    A pair of inverters.
      .    Feedback.

      In order to be an LSSD latch, an L1, which must accept data
from both the combinatorial section (gated by the C clock) and the
previous L1/L2 (gated by the A clock), is required.  Additionally, an
L2 which accepts L1 data, gated by the B clock, is required.
CIRCUIT

      The circuit diagram of Fig. 1 shows a minimal L1/L2 latch with
a single data input.  The input gating is accomplished using pass
N-devices.  The feedback is implemented using P-devices which are on
only when the inputs are turned off.  Leakage through the pass
devices is therefore actively opposed by the feedback device which is
on whenever all clock inputs to a stage are low. Additionally, any
threshold loss suffered by the N-pass device is removed by using
P-device feedback.  The setup time for such an arrangement is about a
nanosecond in CMOSII technology.  Additionally, feedback clocking is
implicit in the P-device structure.  Since all inversion is implicit
in the devices, no extra feedback...