Browse Prior Art Database

Cache Directory with Partial Tag Information

IP.com Disclosure Number: IPCOM000107887D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 47K

Publishing Venue

IBM

Related People

Kahle, JA: AUTHOR [+2]

Abstract

Cache directory is used to store tag information to identify each entry in the cache. It usually contains some high-order bits which are not used to address the cache, plus some other information such as real page number in a real cache or segment ID in a virtual cache. The chip area occupied by the cache directory becomes an important factor in a single-chip processor implementation with on-chip cache. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 90% of the total text.

Cache Directory with Partial Tag Information

      Cache directory is used to store tag information to identify
each entry in the cache.  It usually contains some high-order bits
which are not used to address the cache, plus some other information
such as real page number in a real cache or segment ID in a virtual
cache.  The chip area occupied by the cache directory becomes an
important factor in a single-chip processor implementation with
on-chip cache.

                            (Image Omitted)

      Cache directory with partial tag information is the main
feature of this invention.  In the conventional cache directory
design, directory has to contain complete tag information in order to
identify each cache entry unambiguously.  No false compare is allowed
to occur.  In this invention, an on-chip cache directory is designed
to contain partial tag information to save chip area and an off-chip
directory contains complete tag information which would be the L2
directory, if L2 cache is implemented.  All cache access will use
on-chip directory first to check if partial tags match.  If they
match, this access will be treated as a cache hit, and continues its
execution.  At the same time, tags will be sent to the off-chip
directory to do a full compare to check if it is a false compare.  If
tags do not compare, a false-compare signal will be sent back to the
processor.

      In this system, cache accesses can be reexecuted if t...