Browse Prior Art Database

Device Damage Detection Circuit

IP.com Disclosure Number: IPCOM000107892D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 44K

Publishing Venue

IBM

Related People

York, JL: AUTHOR

Abstract

A device damage detection circuit is shown which utilizes the same I/O pads on a chip that are used to check the chip circuits.

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This is the abbreviated version, containing approximately 100% of the total text.

Device Damage Detection Circuit

      A device damage detection circuit is shown which utilizes the
same I/O pads on a chip that are used to check the chip circuits.

      Without using extra I/O pins on a substrate package, multiple
use of I/O pads on a chip can provide the means for electrically
testing both the chip circuits and detection of device damage
(silicon cracks) after chip to substrate assembly.

      Referring to Fig. 1, a fused conductive diffusion line is shown
around the perimeter of a chip in a wafer, originating at point A and
terminating at point B.  After wafer processing, each device is
checked for diffusion continuity using the solder ball pads at A and
B.  After the wafer is diced, chips are removed for substrate
mounting. Each substrate has lines common to a pair of pads, Fig. 2,
terminating at substrate pins C and D.  At test time, continuity
between I/O lands A and B is checked.  If the chip is cracked during
chip to substrate assembly, the conductive diffusion line is broken
and continuity interrupted.  Thus, device damage is detected.  If no
chip device damage is detected, high voltage between pins C and D is
used to blow the fuse in the diffusion line.  This technique allows
for electrical testing for cracks in the silicon without adding
additional pins to the package.

      Disclosed anonymously.