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CMOS NOR Circuit having Symmetric Delay from Rising Edge of Inputs

IP.com Disclosure Number: IPCOM000107893D
Original Publication Date: 1992-Mar-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 1 page(s) / 29K

Publishing Venue

IBM

Related People

Hiltebeitel, NR: AUTHOR

Abstract

By the addition of two transistors to standard CMOS NOR circuits to make loading at each of two inputs equal, performance of the NOR circuits is no longer dependent on which of the two inputs rises.

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CMOS NOR Circuit having Symmetric Delay from Rising Edge of Inputs

      By the addition of two transistors to standard CMOS NOR
circuits to make loading at each of two inputs equal, performance of
the NOR circuits is no longer dependent on which of the two inputs
rises.

      Referring to the figure, a standard NOR circuit configuration
is comprised of transistors T1, T2, T3, and T4.  Device T5 is added
to quickly discharge node N1 to ground when input IN1 rises, before
the loading of node N1 can slow discharge of output OUT.  Device T6
is added to make the input loading of inputs IN1 and IN2 equal.

      This concept is extendable to three or more inputs and may also
be implemented in CMOS NAND circuits wherein performance can be made
independent of which input falls.

      Disclosed anonymously.