Browse Prior Art Database

Error Correction Circuit for Solid State Disk

IP.com Disclosure Number: IPCOM000107947D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Nijima, H: AUTHOR [+3]

Abstract

Disclosed is an error correction circuit for a solid-state disk. A zero overhead time is achieved for the data read/write operation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 93% of the total text.

Error Correction Circuit for Solid State Disk

       Disclosed is an error correction circuit for a
solid-state disk.  A zero overhead time is achieved for the data
read/write operation.

      Fig. 1(a)  shows the conventional circuit.  There are two
factors in the overhead time, as shown in Fig. 1(b). One is the
parity read/ write time, which increases when a higher capability is
required.  The other is the data buffering delay  for the read
operation.  The sector data are stored into the queue buffer and
cannot be extracted from the circuit until error checking is
finished.

      The proposed circuit and its time chart are shown in Figs. 2(a)
and  2(b).  The memory chips for the parities are separated from
those for the data.  As a result, the parity read/write operation can
be executed independently of the data read/write in the background,
without any overhead time.  The data are directly transferred to the
host computer without  buffering, and error checking is performed at
the same time.  The circuit generates an interrupt signal only when
an error is found.  As a result, a zero overhead time is achieved for
the data read/write operation.

      The proposed circuit has two further advantages:  the amount of
hardware is greatly reduced, because no buffer is necessary, and the
low data error rate of the semiconductor medium allows software error
correction without actual performance loss.  The ratio of parities is
reduced while keeping...