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Self Sealing Structure for Low Temperature Pad Limiting Metallurgy

IP.com Disclosure Number: IPCOM000107948D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Hill, WR: AUTHOR [+2]

Abstract

A method is described which seals the edges of pad limiting metallurgy (PLM) on semiconductor chips. The bottom alloy layer of a bimetallic PLM process may be susceptible to contaminants. A top alloying layer protects the top surface of the bottom layer but leaves the edges exposed. An added thick nitride passivation layer is proposed which forms a self-sealing structure with the top alloy layer.

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Self Sealing Structure for Low Temperature Pad Limiting Metallurgy

       A method is described which seals the edges of pad
limiting metallurgy (PLM) on semiconductor chips. The bottom alloy
layer of a bimetallic PLM process may be susceptible to contaminants.
A top alloying layer protects the top surface of the bottom layer but
leaves the edges exposed. An added thick nitride passivation layer is
proposed which forms a self-sealing structure with the top alloy
layer.

      The first step of the proposed self-sealing method is to add a
thick nitride layer over the chip just prior to adding PLM, as shown
in Fig. 1. Next the nitride is etched through the same photoresist
mask as used to lift off the PLM structure. See Fig. 2. Fig. 3 shows
that a pad bonding alloy deposited in the bottom of each opened hole
is followed by a top alloy. The top alloy expands against the thick
nitride layer to form a tight seal over the entire bottom alloy. The
additional thick nitride layer is the principal deviation from
conventional processing and is responsible for the self-sealing
capability.