Browse Prior Art Database

Alternate Chip/ Substrate Interconnection Technology

IP.com Disclosure Number: IPCOM000107950D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Potter, MD: AUTHOR [+3]

Abstract

A technique is described for connecting a semiconductor chip to a ceramic substrate by means of metallized studs on the chip which are soldered into partially solder-filled contact holes on the substrate. Both the chip and substrate terminal pads are formed using conventional semiconductor lithographic pattern definition, metallization and planarization techniques. Studs contacting the chip pads are formed by plating or evaporating a suitable metal through contact holes in a lithography-defined stencil. Solder contacting the substrate pads is deposited through contact holes in a photoresist. The chip studs are inserted into corresponding substrate contact holes, and the assembly is heated to melt the solder and make electrical connections between chip and substrate.

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Alternate Chip/ Substrate Interconnection Technology

       A technique is described for connecting a semiconductor
chip to a ceramic substrate by means of metallized studs on the chip
which are soldered into partially solder-filled contact holes on the
substrate.  Both the chip and substrate terminal pads are formed
using conventional semiconductor lithographic pattern definition,
metallization and planarization techniques. Studs contacting the chip
pads are formed by plating or evaporating a suitable metal through
contact holes in a lithography-defined stencil. Solder contacting the
substrate pads is deposited through contact holes in a photoresist.
The chip studs are inserted into corresponding substrate contact
holes, and the assembly is heated to melt the solder and make
electrical connections between chip and substrate.

      Normal semiconductor processes are used to fabricate the chip
through the final metal wiring level. This wiring level is then
passivated with a suitable insulator, such as silicon dioxide, and a
stencil defined by lithography is layered over the passivated
surface.  Contact holes are opened to the chip terminal pads using
standard processes. A suitable metal is deposited over the chip
surface so that metal studs are formed in the contact holes to
contact the pads. See Fig. 1. When the surface stud metal and the
stencil are removed, the terminal studs protrude above the insulator.

      In a similar manner, the metal pattern on th...