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Browse Prior Art Database

Pseudo Asynchronous Bus Interface

IP.com Disclosure Number: IPCOM000107974D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 2 page(s) / 98K

Publishing Venue

IBM

Related People

Borkenhagen, JM: AUTHOR [+2]

Abstract

A bus interface that combines the advantages of synchronous and asynchronous interfaces is disclosed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Pseudo Asynchronous Bus Interface

       A bus interface that combines the advantages of
synchronous and asynchronous interfaces is disclosed.

      Clock skew is added as overhead for each transfer on a
synchronous bus.  Clock skew overhead on timing critical buses
results in a direct adder to processor cycle time.

      There is no required relationship between the clocks of two
chips on an asynchronous bus.  Chip-to-chip clock skew overhead does
not have to be added to data transfers on an asynchronous bus.

      An asynchronous bus requires point-to-point nets to send a
clock with data.  The clock is used to latch data into the receiving
logic.  The transmission line effects of point-to-point nets can be
well controlled, allowing new data to be sent before the previous
data has reached the end of the bus.  This method of pumping data
onto a bus results in better bus bandwidth compared to a synchronous
bus.

      A drawback of asynchronous buses is the introduction of latency
required for synchronization on the receiving chip. Latch
metastability errors would occur if the data were not synchronized.
The synchronization latency can result in unacceptable performance
degradation on buses where data transfers are done in small packets.

      To help understand this disclosure, consider two chips that
have synchronous clocks with a bus to transfer data between them.
The sending chip generates a clock signal and sends it down the
interconnecting bus with data.  The clock signal loads data into a
register on the receiving chip.  By considering the clock used to
load bus data into the receiving chip to be asynchronous to the
receiving chip, clock skew between chips can be ignored for the
asynchronous register load.  Subsequent clock signals are sent down
the bus with their associated data.  Each clock loads its data into a
receiving register.  The number of registers required to receive data
is determined by the number of data bus transfers desired before
transferring data from the asynchronously clocked registers into
synchronously clocked registers.

      Data will be valid and stable in the asynchronous receiving
registers, with reference to the synchronous clocks at the receiving
chip, at a measured time equal to t...