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Browse Prior Art Database

Inhibiting Large Current Draw on CMOS Chips during LSSD Scan

IP.com Disclosure Number: IPCOM000107980D
Original Publication Date: 1992-Apr-01
Included in the Prior Art Database: 2005-Mar-22
Document File: 4 page(s) / 137K

Publishing Venue

IBM

Related People

Marquart, DW: AUTHOR [+2]

Abstract

Scanning a chip using LSSD (Level-Sensitive Scan Design) or other scan technologies shifts data through all of the latches on an LSSD chip. Unless all of the data bits shifted through the LSSD scan ring are the same value, this causes the logic nets fed by each LSSD latch to switch every time a different value appears in the latch. In most bipolar chips, this does not matter. In CMOS chips with low shift speeds, it does not matter either. However, if the scan path is used in a machine for access to logic values or for testing and the shift speed is high (100 nanoseconds per bit or faster), CMOS chips end up switching most of the nets and logic blocks on the chip during every scan cycle.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Inhibiting Large Current Draw on CMOS Chips during LSSD Scan

       Scanning a chip using LSSD (Level-Sensitive Scan Design)
or other scan technologies shifts data through all of the latches on
an LSSD chip.  Unless all of the data bits shifted through the LSSD
scan ring are the same value, this causes the logic nets fed by each
LSSD latch to switch every time a different value appears in the
latch.  In most bipolar chips, this does not matter.  In CMOS chips
with low shift speeds, it does not matter either.  However, if the
scan path is used in a machine for access to logic values or for
testing and the shift speed is high (100 nanoseconds per bit or
faster), CMOS chips end up switching most of the nets and logic
blocks on the chip during every scan cycle.  Because CMOS power
requirements depend on the amount of switching, this affects the
power requirements and generates noise on the power supply.

      The solution to the problem is to prevent the propagation of
data scanned through a scan path to the logic of the chip.  That is,
during scan, the latches of the scan path must not allow the changing
data to pass out of the latch.

      On large chips, there is a restriction on the number of
off-chip drivers that can switch at one time.  Chip designers must
take care that normal operation of the chip does not violate this
restriction.  During scan, the restrictions could be violated,
possibly causing the chip to fail to operate correctly.  Some CMOS
technologies provide a pin, often called Driver Inhibit, that causes
all drivers not involved in scanning (such as Scan Data Out and
repowered scan clocks) to be in the high-impedance state.  The
solution to the scan power problem is related to the Driver Inhibit
solution for drivers.

      A signal received by the chip, or created by logic from a set
of signals received by the chip, determines whether the chip is being
scanned.  The Scan In Progress signal is connected to all latches on
the chip much like the scan clocks are connected to all latches.
Scan In Progress causes latches to drive all functional outputs from
the latch to a constant value.  The constant value can be 1 or 0; it
does not matter which as long as it is constant.

      This invention reduces power demand during scanning by stopping
the outputs of the latches from switching, which stops the
combinational logic using the outputs from switching.  CMOS gates use
power when they switch, not when they receive unchanging inputs
(ex...